1. Field of the Invention
The present invention relates to a liquid crystal display device and a fabrication method thereof, and more particularly, to a liquid crystal display device and a fabrication method thereof with an improved yield by preventing disconnection between conductive layers, and a fabrication method thereof.
2. Discussion of the Related Art
Recently, information displays including portable information displays have drawn great attention. Accordingly, thin and light-weight flat panel display (FPD) devices have been actively researched and commercialized to replace existing cathode ray tubes (CRTs). In particular, among various FPD devices, liquid crystal display (LCD) devices have been widely used as a device for displaying images by using optical anisotropic properties of liquid crystals. For example, LCD devices are currently used in notebook computers and desktop monitors due to their superior resolution, color rendering capability, and image quality.
An LCD device generally includes a first substrate (e.g., a color filter substrate), a second substrate (e.g., an array substrate), and a liquid crystal layer disposed between the two substrates. FIG. 1 is a perspective view schematically showing a related art LCD device. As shown in FIG. 1, the LCD device includes a color filter substrate 5, an array substrate 10, and a liquid crystal layer 40 disposed between the color filter substrate 5 and the array substrate 10. The color filter substrate 5 includes a color filter C having a plurality of sub-color filters 7 for rendering colors R (Red), G (Green) and B (Blue). Also, the color filter substrate 5 has a black matrix 6 disposed between the sub-color filters 7 for preventing light from being transmitted through the liquid crystal layer 40, and a transparent common electrode 8 for applying a voltage to the liquid crystal layer 40. The array substrate 10 includes a plurality of gate lines 16 and data lines 17 arranged in horizontal and vertical directions, respectively. The gate lines 16 and data lines 17 define a plurality of pixel regions P, and pixel electrodes 18 are formed on the pixel regions P. Thin film transistors T, which are used as switching devices, are formed at each intersection between the gate lines 16 and data lines 17. The color filter substrate 5 and the array substrate 10 having such construction are bonded facing each other by a sealant (not shown) formed at a periphery of an image display region to form an LCD panel. The color filter substrate 5 and the array substrate 10 are bonded to each other by use of a bonding key (not shown) formed on either the color filter substrate 5 or the array substrate 10.
During fabrication, various layers are formed on the respective substrates to construct the LCD device. For instance, an upper layer is usually arranged on top of a lower layer sometimes crossing the lower layer. When a taper, i.e. an inclined angle of the lower layer is formed improperly, a disconnection may occur between the upper layer and the lower layer during patterning of the upper layer.
FIGS. 2A through 2C are plane views showing sequential processes of a pattern forming method according to the related art that illustrates forming a gate electrode on an active pattern. In addition, FIGS. 3A through 3C are cross-sectional views showing the sequential processes of the pattern forming method according to the related art. In particular, the cross-sectional views are taken along the line A-A′ of FIGS. 2A through 2C, and sequentially illustrate the pattern forming method shown in FIGS. 2A through 2C.
As shown in FIGS. 2A and 3A, an active pattern 24, which is formed of a thin silicon film, is formed on a substrate 10. As shown in FIGS. 2B and 3B, an insulating film 15A and a conductive layer 20 are sequentially deposited on an entire surface of the substrate 10. Here, when the taper of the active pattern 24, i.e. the lower layer, is properly formed, the conductive layer 20, i.e. the upper layer, is deposited properly. The term “taper” is to be construed as an inclined angle of a patterned layer. Conversely, when the taper of the active pattern 24 is improperly formed, a void V is formed at an interface between the conductive layer 20 and the active pattern 24. When a void V is formed, an etching solution may flow into the void V during photolithographic patterning process of the conductive layer 20. As a result, the etching solution may cause a disconnection D in the gate electrode 21 upon patterning the gate electrode 21, as shown in FIGS. 2C and 3C. In particular, the disconnection D in the upper layer is frequently caused when the upper layer is formed by wet etching with the taper of the lower layer being improperly formed.